JTAG Investigation

The 2x5 pin header on the USB/controller board is our path to the LPC2103F’s 32KB flash — the firmware that orchestrates everything this amplifier does. Getting JTAG working is the highest-priority investigation task.

First contact

I connected a Treedix DAP-Link V1 (CMSIS-DAP compatible) debug probe to the 2x5 header using a NOYITO 2.0mm-to-2.54mm pitch adapter board. The adapter converts the 2.0mm header pitch to standard 2.54mm breadboard spacing, in theory allowing a standard 20-pin ribbon cable to reach the smaller header.

OpenOCD with the cmsis-dap interface config and lpc2103.cfg target config should produce a clean connection to the ARM7TDMI-S core. The expected JTAG TAP IDCODE for the LPC2103 is 0x4F1F0F0F.

What actually happened

Configuration	Adapter Speed	IDCODE Returned	Observation
mcjtag MCP	1500 kHz	0x00000001	20 phantom TAPs detected, not real
Raw OpenOCD	1500 kHz	0x00000001	Same result — proves mcjtag is not the problem
Raw OpenOCD	100 kHz	All zeros	TDO stuck low, no response at all
SWD mode	100 kHz	Connected	But ARM7TDMI has no SWD support — JTAG only
urjtag	N/A	N/A	No CMSIS-DAP driver available

The 0x00000001 IDCODE at high speed is a classic symptom of a JTAG chain that is electrically connected but with signals on the wrong pins. The TAP state machine is cycling, but TDI and TDO are not reaching the correct MCU pins. At low speed the problem manifests differently — TDO stays low, suggesting it is not connected at all or is being driven by a non-JTAG pin on the MCU.

Root cause: the adapter

The NOYITO 2.0mm-to-2.54mm adapter board is scrambling the pin mapping. The ARM JTAG 20-pin header has a specific signal assignment (TCK on pin 9, TMS on pin 7, TDI on pin 5, TDO on pin 13, and so on), but the adapter appears to be a simple geometric pitch converter — it maps physical positions from one pitch to another without following the ARM JTAG signal standard. The result is that the debug probe’s TDI output arrives at the wrong MCU pin, its TCK drives something that is not the clock input, and the actual TDO pin’s output goes to a pin the probe is not reading.

Cheap adapters, expensive debugging

This is a common pitfall with off-brand JTAG adapters. A proper pitch adapter must preserve the signal-to-pin mapping defined by the ARM debug connector standard, not just convert physical dimensions. The fix is to bypass the adapter entirely and wire each signal individually.

The fix: direct wiring

The path forward is to buzz out the 2x5 header with a multimeter, mapping each header pin to its corresponding LPC2103F signal by probing continuity against the MCU’s LQFP48 pads. Once the mapping is known, DuPont jumper wires from the DAP-Link to the correct header pins will bypass the adapter completely.

LPC2103F JTAG pinout (verified)

The JTAG pin assignments for the LPC2103FBD48 in the LQFP48 package, verified against the NXP datasheet and confirmed by tracing the Olimex LPC-H2103 reference schematic:

Signal	GPIO	LQFP48 Pin	Description
nRESET	—	6	Active-low reset
TRST	P0.27	8	Test Reset
TMS	P0.28	9	Test Mode Select
TCK	P0.29	10	Test Clock (must be less than CCLK/6)
TDI	P0.30	15	Test Data In
TDO	P0.31	16	Test Data Out (output only pin)
RTCK	—	26	Return Test Clock
DBGSEL	—	27	Debug Select (HIGH enables EmbeddedICE)

When DBGSEL is driven HIGH, pins P0.27 through P0.31 are automatically configured for JTAG debugging regardless of the pin function select registers. This means the JTAG interface works even if the firmware has reconfigured those pins as GPIO.

Power and ground pins nearby, useful for continuity reference during buzzing:

Signal	LQFP48 Pin
VDD(1V8)	5
VSS (GND)	7
VDD(3V3)	17
VSS (GND)	19

Standard ARM 20-pin JTAG header

For reference, the standard ARM JTAG 20-pin connector places signals on odd pins and ground on even pins:

          ┌───────────┐
    VREF  │ 1      2  │ VTARGET
    nTRST │ 3      4  │ GND
    TDI   │ 5      6  │ GND
    TMS   │ 7      8  │ GND
    TCK   │ 9     10  │ GND
    RTCK  │11     12  │ GND
    TDO   │13     14  │ GND
    nRST  │15     16  │ GND
    DBGRQ │17     18  │ GND
    DBGACK│19     20  │ GND
          └───────────┘
           (PCB top view)

The Episode amp’s 2x5 header at 2.0mm pitch is a condensed version of this — likely a subset of the 20-pin standard or a vendor-specific layout. The actual mapping will be determined by the multimeter buzzing.

Buzzing strategy

Set the multimeter to continuity mode. Start by probing for ground: touch one lead to a known ground point on the board (any large copper pour or the metal chassis) and probe each of the 10 header pins. Every GND pin will beep. Then switch to probing the remaining pins against the LPC2103F’s LQFP48 pads — pin 8 for TRST, pin 9 for TMS, pin 10 for TCK, pin 15 for TDI, pin 16 for TDO, and pin 6 for nRESET. Pins 26 (RTCK) and 27 (DBGSEL) round out the set.

Once the mapping is complete, wire DuPont jumpers directly from the DAP-Link’s 20-pin header to the correct 2x5 header pins and retry the OpenOCD connection. The expected IDCODE is 0x4F1F0F0F.

OpenOCD configuration

The working config file for when JTAG is properly connected:

openocd-daplink-lpc2103.cfg

source [find interface/cmsis-dap.cfg]
transport select jtag
adapter speed 100
reset_config none
source [find target/lpc2103.cfg]

The reset_config none override is necessary because no reset lines are connected on this cable — pure JTAG signals only. The stock lpc2103.cfg expects trst_and_srst, which would cause OpenOCD to fail without the override. Start at 100 kHz for first contact, then increase speed after the connection is confirmed.